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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/CampregherCCV06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Milan_Vasilko>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nicola_Campregher>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1117201.1117215>
foaf:homepage <https://doi.org/10.1145/1117201.1117215>
dc:identifier DBLP conf/fpga/CampregherCCV06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1117201.1117215 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Yield enhancements of design-specific FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Milan_Vasilko>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nicola_Campregher>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
swrc:pages 93-100 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/CampregherCCV06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/CampregherCCV06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2006.html#CampregherCCV06>
rdfs:seeAlso <https://doi.org/10.1145/1117201.1117215>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA interconnect, design-specific FPGA, interconnect faults, interconnect utilization, structured ASIC, yield enhancement, yield prediction (xsd:string)
dc:title Yield enhancements of design-specific FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document