3D configuration caching for 2D FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/CevreroAPBLIS09
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2009
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3D configuration caching for 2D FPGAs.
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3d integration, configuration caching, field programmable gate array (fpga), reconfigurable computing
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3D configuration caching for 2D FPGAs.
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