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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/ChanL96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_M._Lewis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vi_Cuong_Chan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F228370.228378>
foaf:homepage <https://doi.org/10.1145/228370.228378>
dc:identifier DBLP conf/fpga/ChanL96 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F228370.228378 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_M._Lewis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vi_Cuong_Chan>
swrc:pages 51-57 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/ChanL96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/ChanL96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga96.html#ChanL96>
rdfs:seeAlso <https://doi.org/10.1145/228370.228378>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document