Architectural Enhancements in Intel¬ģ Agilex‚ĄĘ FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/ChromczakWCHLVZ20
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/fpga/ChromczakWCHLVZ20
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Charles_Chiasson
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Dana_How
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Grace_Zgheib
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ilya_Ganusov
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Chromczak
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Wheeler
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Martin_Langhammer
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tim_Vanderhoek
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F3373087.3375308
>
foaf:
homepage
<
https://doi.org/10.1145/3373087.3375308
>
dc:
identifier
DBLP conf/fpga/ChromczakWCHLVZ20
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F3373087.3375308
(xsd:string)
dcterms:
issued
2020
(xsd:gYear)
rdfs:
label
Architectural Enhancements in Intel¬ģ Agilex‚ĄĘ FPGAs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Charles_Chiasson
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Dana_How
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Grace_Zgheib
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ilya_Ganusov
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Chromczak
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Wheeler
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Martin_Langhammer
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tim_Vanderhoek
>
swrc:
pages
140-149
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2020
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/fpga/ChromczakWCHLVZ20/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/fpga/ChromczakWCHLVZ20
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/fpga/fpga2020.html#ChromczakWCHLVZ20
>
rdfs:
seeAlso
<
https://doi.org/10.1145/3373087.3375308
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/fpga
>
dc:
title
Architectural Enhancements in Intel¬ģ Agilex‚ĄĘ FPGAs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document