[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/DaigneaultD10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean-Pierre_David>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marc-Andr%E2%88%9A%C2%A9_Daigneault>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1723112.1723161>
foaf:homepage <https://doi.org/10.1145/1723112.1723161>
dc:identifier DBLP conf/fpga/DaigneaultD10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1723112.1723161 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean-Pierre_David>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marc-Andr%E2%88%9A%C2%A9_Daigneault>
swrc:pages 283 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/DaigneaultD10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/DaigneaultD10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2010.html#DaigneaultD10>
rdfs:seeAlso <https://doi.org/10.1145/1723112.1723161>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject dynamic reconfiguration, field programmable gate array, time-to-digital converter, vernier method (xsd:string)
dc:title Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document