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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/EjniouiR99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abdel_Ejnioui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F296399.296454>
foaf:homepage <https://doi.org/10.1145/296399.296454>
dc:identifier DBLP conf/fpga/EjniouiR99 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F296399.296454 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abdel_Ejnioui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
swrc:pages 176-185 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/EjniouiR99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/EjniouiR99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga99.html#EjniouiR99>
rdfs:seeAlso <https://doi.org/10.1145/296399.296454>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA architecture, FPGA routing, branch-and-price, integer programming, interconnect optimization, layout synthesis (xsd:string)
dc:title Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document