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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/HallschmidW01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Hallschmid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steven_J._E._Wilton>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F360276.360300>
foaf:homepage <https://doi.org/10.1145/360276.360300>
dc:identifier DBLP conf/fpga/HallschmidW01 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F360276.360300 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Detailed routing architectures for embedded programmable logic IP cores. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Hallschmid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steven_J._E._Wilton>
swrc:pages 69-74 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/HallschmidW01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/HallschmidW01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2001.html#HallschmidW01>
rdfs:seeAlso <https://doi.org/10.1145/360276.360300>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, SoC design, detailed routing, embedded cores, programmable logic (xsd:string)
dc:title Detailed routing architectures for embedded programmable logic IP cores. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document