Large-scale wire-speed packet classification on FPGAs. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/fpga/JiangP09>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Weirong_Jiang>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1508128.1508162>
foaf:homepage	<https://doi.org/10.1145/1508128.1508162>
dc:identifier	DBLP conf/fpga/JiangP09 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1508128.1508162 (xsd:string)
dcterms:issued	2009 (xsd:gYear)
rdfs:label	Large-scale wire-speed packet classification on FPGAs. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Weirong_Jiang>
swrc:pages	219-228 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2009>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/fpga/JiangP09/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/fpga/JiangP09>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/fpga/fpga2009.html#JiangP09>
rdfs:seeAlso	<https://doi.org/10.1145/1508128.1508162>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject	decision tree, fpga, packet classification, pipeline, sram (xsd:string)
dc:title	Large-scale wire-speed packet classification on FPGAs. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document