Voter insertion algorithms for FPGA designs using triple modular redundancy.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/JohnsonW10
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/fpga/JohnsonW10
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jonathan_M._Johnson
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Michael_J._Wirthlin
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1723112.1723154
>
foaf:
homepage
<
https://doi.org/10.1145/1723112.1723154
>
dc:
identifier
DBLP conf/fpga/JohnsonW10
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1723112.1723154
(xsd:string)
dcterms:
issued
2010
(xsd:gYear)
rdfs:
label
Voter insertion algorithms for FPGA designs using triple modular redundancy.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jonathan_M._Johnson
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Michael_J._Wirthlin
>
swrc:
pages
249-258
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2010
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/fpga/JohnsonW10/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/fpga/JohnsonW10
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/fpga/fpga2010.html#JohnsonW10
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1723112.1723154
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/fpga
>
dc:
subject
algorithm, fpga, reliability, scc, synchronization, tmr, voter insertion
(xsd:string)
dc:
title
Voter insertion algorithms for FPGA designs using triple modular redundancy.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document