Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/KolligA99
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1999
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Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.
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FPGA, bit-level pipelined, circuit latency, recursive algorithms
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Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.
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