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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/KolligA99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bashir_M._Al-Hashimi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Kollig>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F296399.296466>
foaf:homepage <https://doi.org/10.1145/296399.296466>
dc:identifier DBLP conf/fpga/KolligA99 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F296399.296466 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bashir_M._Al-Hashimi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Kollig>
swrc:pages 227-234 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/KolligA99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/KolligA99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga99.html#KolligA99>
rdfs:seeAlso <https://doi.org/10.1145/296399.296466>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, bit-level pipelined, circuit latency, recursive algorithms (xsd:string)
dc:title Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document