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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/LyC09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Le_Ly>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_Chow>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1508128.1508140>
foaf:homepage <https://doi.org/10.1145/1508128.1508140>
dc:identifier DBLP conf/fpga/LyC09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1508128.1508140 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A high-performance FPGA architecture for restricted boltzmann machines. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Le_Ly>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_Chow>
swrc:pages 73-82 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/LyC09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/LyC09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2009.html#LyC09>
rdfs:seeAlso <https://doi.org/10.1145/1508128.1508140>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject complexity reduction, fpga, high-performance computing, neural network hardware, restricted boltzmann machines, scalable hardware designs (xsd:string)
dc:title A high-performance FPGA architecture for restricted boltzmann machines. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document