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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/PalchaudhuriSD20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sandeep_Sharma>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3373087.3375335>
foaf:homepage <https://doi.org/10.1145/3373087.3375335>
dc:identifier DBLP conf/fpga/PalchaudhuriSD20 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3373087.3375335 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sandeep_Sharma>
swrc:pages 316 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/PalchaudhuriSD20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/PalchaudhuriSD20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2020.html#PalchaudhuriSD20>
rdfs:seeAlso <https://doi.org/10.1145/3373087.3375335>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document