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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/Parandeh-AfsharBI08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hadi_Parandeh-Afshar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Ienne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_Brisk>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1344671.1344698>
foaf:homepage <https://doi.org/10.1145/1344671.1344698>
dc:identifier DBLP conf/fpga/Parandeh-AfsharBI08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1344671.1344698 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label A novel FPGA logic block for improved arithmetic performance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hadi_Parandeh-Afshar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Ienne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_Brisk>
swrc:pages 171-180 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/Parandeh-AfsharBI08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/Parandeh-AfsharBI08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2008.html#Parandeh-AfsharBI08>
rdfs:seeAlso <https://doi.org/10.1145/1344671.1344698>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject 6.2 compressor, FPGA, arithmetic circuits, carry-chain, compressor tree, multi-operand addition (xsd:string)
dc:title A novel FPGA logic block for improved arithmetic performance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document