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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/PellauerVAAE08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arvind>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joel_S._Emer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Adler>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Pellauer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muralidaran_Vijayaraghavan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1344671.1344685>
foaf:homepage <https://doi.org/10.1145/1344671.1344685>
dc:identifier DBLP conf/fpga/PellauerVAAE08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1344671.1344685 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arvind>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joel_S._Emer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Adler>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Pellauer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muralidaran_Vijayaraghavan>
swrc:pages 87-96 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/PellauerVAAE08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/PellauerVAAE08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2008.html#PellauerVAAE08>
rdfs:seeAlso <https://doi.org/10.1145/1344671.1344685>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, emulation, performance models, prototyping, simulation (xsd:string)
dc:title A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document