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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/RitterM01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%E2%88%82rg_Ritter_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_Molitor>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F360276.360350>
foaf:homepage <https://doi.org/10.1145/360276.360350>
dc:identifier DBLP conf/fpga/RitterM01 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F360276.360350 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%E2%88%82rg_Ritter_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_Molitor>
swrc:pages 201-206 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/RitterM01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/RitterM01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2001.html#RitterM01>
rdfs:seeAlso <https://doi.org/10.1145/360276.360350>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, Xilinx, architecture, embedded zero tree coding, field programmable gate arrays, lossy image compression, pipelining, wavelet transformation (xsd:string)
dc:title A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document