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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/RobertsonILR02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Robinson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ian_Robertson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Irvine_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Patrick_Lysaght>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F503048.503068>
foaf:homepage <https://doi.org/10.1145/503048.503068>
dc:identifier DBLP conf/fpga/RobertsonILR02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F503048.503068 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Robinson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ian_Robertson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Irvine_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Patrick_Lysaght>
swrc:pages 127-135 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/RobertsonILR02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/RobertsonILR02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2002.html#RobertsonILR02>
rdfs:seeAlso <https://doi.org/10.1145/503048.503068>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, dynamic reconfiguration, run-time reconfiguration, verification (xsd:string)
dc:title Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document