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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/RoseLYDGSKJA12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrew_Somerville>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chi_Wai_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Helge_Anderson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Luu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Goeders>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Rose>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kenneth_B._Kent>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Opal_Densmore>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Jamieson>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F2145694.2145708>
foaf:homepage <https://doi.org/10.1145/2145694.2145708>
dc:identifier DBLP conf/fpga/RoseLYDGSKJA12 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F2145694.2145708 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label The VTR project: architecture and CAD for FPGAs from verilog to routing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrew_Somerville>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chi_Wai_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Helge_Anderson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Luu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Goeders>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Rose>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kenneth_B._Kent>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Opal_Densmore>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Jamieson>
swrc:pages 77-86 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/RoseLYDGSKJA12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/RoseLYDGSKJA12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2012.html#RoseLYDGSKJA12>
rdfs:seeAlso <https://doi.org/10.1145/2145694.2145708>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title The VTR project: architecture and CAD for FPGAs from verilog to routing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document