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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/SchelleCSWZCPMOHSBSW10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ethan_Schuchman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Franz_Olbrich>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gautham_N._Chinya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Graham_Schelle>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hong_Wang_0003>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jamison_D._Collins>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jim_Brayton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Per_Hammarlund>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Perry_H._Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ralf_Plate>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronak_Singhal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sebastian_Steibl>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thorsten_Mattner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang_Zou>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1723112.1723116>
foaf:homepage <https://doi.org/10.1145/1723112.1723116>
dc:identifier DBLP conf/fpga/SchelleCSWZCPMOHSBSW10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1723112.1723116 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Intel nehalem processor core made FPGA synthesizable. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ethan_Schuchman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Franz_Olbrich>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gautham_N._Chinya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Graham_Schelle>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hong_Wang_0003>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jamison_D._Collins>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jim_Brayton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Per_Hammarlund>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Perry_H._Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ralf_Plate>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronak_Singhal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sebastian_Steibl>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thorsten_Mattner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang_Zou>
swrc:pages 3-12 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/SchelleCSWZCPMOHSBSW10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/SchelleCSWZCPMOHSBSW10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2010.html#SchelleCSWZCPMOHSBSW10>
rdfs:seeAlso <https://doi.org/10.1145/1723112.1723116>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject emulator, fpga, intel nehalem, synthesizable core (xsd:string)
dc:title Intel nehalem processor core made FPGA synthesizable. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document