Constrained clock shifting for field programmable gate arrays. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/fpga/SinghB02a>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Deshanand_P._Singh>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Stephen_Dean_Brown>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F503048.503067>
foaf:homepage	<https://doi.org/10.1145/503048.503067>
dc:identifier	DBLP conf/fpga/SinghB02a (xsd:string)
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dcterms:issued	2002 (xsd:gYear)
rdfs:label	Constrained clock shifting for field programmable gate arrays. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Deshanand_P._Singh>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Stephen_Dean_Brown>
swrc:pages	121-126 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/fpga/fpga2002.html#SinghB02a>
rdfs:seeAlso	<https://doi.org/10.1145/503048.503067>
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dc:title	Constrained clock shifting for field programmable gate arrays. (xsd:string)
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rdf:type	swrc:InProceedings
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