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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/SioziosTST06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonios_Thanailakis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Soudris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Konstantinos_Tatas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kostas_Siozios>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1117201.1117236>
foaf:homepage <https://doi.org/10.1145/1117201.1117236>
dc:identifier DBLP conf/fpga/SioziosTST06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1117201.1117236 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A novel methodology for designing high-performance and low-energy FPGA routing architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonios_Thanailakis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Soudris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Konstantinos_Tatas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kostas_Siozios>
swrc:pages 224 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/SioziosTST06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/SioziosTST06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2006.html#SioziosTST06>
rdfs:seeAlso <https://doi.org/10.1145/1117201.1117236>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title A novel methodology for designing high-performance and low-energy FPGA routing architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document