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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/TakataM10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Taiga_Takata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Matsunaga>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1723112.1723179>
foaf:homepage <https://doi.org/10.1145/1723112.1723179>
dc:identifier DBLP conf/fpga/TakataM10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1723112.1723179 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Taiga_Takata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Matsunaga>
swrc:pages 289 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/TakataM10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/TakataM10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2010.html#TakataM10>
rdfs:seeAlso <https://doi.org/10.1145/1723112.1723179>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject fpga, technology mapping (xsd:string)
dc:title A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document