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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/TeehanLG09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guy_G._Lemieux>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_R._Greenstreet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_Teehan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1508128.1508136>
foaf:homepage <https://doi.org/10.1145/1508128.1508136>
dc:identifier DBLP conf/fpga/TeehanLG09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1508128.1508136 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guy_G._Lemieux>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_R._Greenstreet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_Teehan>
swrc:pages 43-52 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/TeehanLG09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/TeehanLG09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2009.html#TeehanLG09>
rdfs:seeAlso <https://doi.org/10.1145/1508128.1508136>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject bit-serial, fpga, interconnect, network-on-chip, on-chip serdes, programmable, reliable, surfing, wave pipelining (xsd:string)
dc:title Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document