Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/TeehanLG09
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2009
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Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.
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bit-serial, fpga, interconnect, network-on-chip, on-chip serdes, programmable, reliable, surfing, wave pipelining
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Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.
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