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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/WangYSS14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donghoon_Yeo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyunchul_Shin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muhammad_Sohail_0003>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Wang_0136>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F2554688.2554727>
foaf:homepage <https://doi.org/10.1145/2554688.2554727>
dc:identifier DBLP conf/fpga/WangYSS14 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F2554688.2554727 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Control signal aware slice-level window based legalization method for FPGA placement (abstract only). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donghoon_Yeo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyunchul_Shin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muhammad_Sohail_0003>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Wang_0136>
swrc:pages 249 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/WangYSS14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/WangYSS14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2014.html#WangYSS14>
rdfs:seeAlso <https://doi.org/10.1145/2554688.2554727>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title Control signal aware slice-level window based legalization method for FPGA placement (abstract only). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document