Post-placement C-slow retiming for the xilinx virtex FPGA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/WeaverMPW03
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2003
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Post-placement C-slow retiming for the xilinx virtex FPGA.
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C-slow retiming, FPGA CAD, FPGA optimization, retiming
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Post-placement C-slow retiming for the xilinx virtex FPGA.
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