Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/XiaoLZ024
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/fpga/XiaoLZ024
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kexing_Zhou
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Youwei_Xiao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yun_Liang_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zizhang_Luo
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F3626202.3637561
>
foaf:
homepage
<
https://doi.org/10.1145/3626202.3637561
>
dc:
identifier
DBLP conf/fpga/XiaoLZ024
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F3626202.3637561
(xsd:string)
dcterms:
issued
2024
(xsd:gYear)
rdfs:
label
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kexing_Zhou
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Youwei_Xiao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yun_Liang_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zizhang_Luo
>
swrc:
pages
211-222
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2024
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/fpga/XiaoLZ024/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/fpga/XiaoLZ024
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#XiaoLZ024
>
rdfs:
seeAlso
<
https://doi.org/10.1145/3626202.3637561
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/fpga
>
dc:
title
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document