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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/XuLSL024>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hai_Jin_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaoxian_Xu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sitong_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaofei_Liao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhiyuan_Shao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3626202.3637571>
foaf:homepage <https://doi.org/10.1145/3626202.3637571>
dc:identifier DBLP conf/fpga/XuLSL024 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3626202.3637571 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
rdfs:label MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hai_Jin_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaoxian_Xu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sitong_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaofei_Liao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhiyuan_Shao>
swrc:pages 22-32 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2024>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/XuLSL024/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/XuLSL024>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#XuLSL024>
rdfs:seeAlso <https://doi.org/10.1145/3626202.3637571>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document