[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/YeR05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andy_Gean_Ye>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Rose>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1046192.1046194>
foaf:homepage <https://doi.org/10.1145/1046192.1046194>
dc:identifier DBLP conf/fpga/YeR05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1046192.1046194 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andy_Gean_Ye>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Rose>
swrc:pages 3-13 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/YeR05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/YeR05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2005.html#YeR05>
rdfs:seeAlso <https://doi.org/10.1145/1046192.1046194>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA architecture, area efficiency, datapath regularity, reconfigurable fabric, routing architecture (xsd:string)
dc:title Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document