Bit-level optimization for high-level synthesis and FPGA-based acceleration.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpga/ZhangZZTLCC10
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Bit-level optimization for high-level synthesis and FPGA-based acceleration.
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bit-level optimization, fpga, high-level synthesis
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Bit-level optimization for high-level synthesis and FPGA-based acceleration.
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