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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/ZhouGDZSJFLLVWZ18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gai_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gustavo_Angarita_Velasquez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hanchen_Jin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joseph_Featherston>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nitish_Kumar_Srivastava>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ritchie_Zhao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steve_Dai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Udit_Gupta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wenping_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi-Hsiang_Lai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuan_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhiru_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3174243.3174255>
foaf:homepage <https://doi.org/10.1145/3174243.3174255>
dc:identifier DBLP conf/fpga/ZhouGDZSJFLLVWZ18 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3174243.3174255 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gai_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gustavo_Angarita_Velasquez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hanchen_Jin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joseph_Featherston>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nitish_Kumar_Srivastava>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ritchie_Zhao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steve_Dai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Udit_Gupta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wenping_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi-Hsiang_Lai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuan_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhiru_Zhang>
swrc:pages 269-278 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/ZhouGDZSJFLLVWZ18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/ZhouGDZSJFLLVWZ18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2018.html#ZhouGDZSJFLLVWZ18>
rdfs:seeAlso <https://doi.org/10.1145/3174243.3174255>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:title Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document