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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpga/ZhuoP05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1046192.1046202>
foaf:homepage <https://doi.org/10.1145/1046192.1046202>
dc:identifier DBLP conf/fpga/ZhuoP05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1046192.1046202 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Sparse Matrix-Vector multiplication on FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
swrc:pages 63-74 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpga/ZhuoP05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpga/ZhuoP05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpga/fpga2005.html#ZhuoP05>
rdfs:seeAlso <https://doi.org/10.1145/1046192.1046202>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject FPGA, floating-point, high performance, reconfigurable architecture, sparse matrix (xsd:string)
dc:title Sparse Matrix-Vector multiplication on FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document