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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/AsaadW98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_W._Warren>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sameh_W._Asaad>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2FBFb0055255>
foaf:homepage <https://doi.org/10.1007/BFb0055255>
dc:identifier DBLP conf/fpl/AsaadW98 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2FBFb0055255 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_W._Warren>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sameh_W._Asaad>
swrc:pages 278-287 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/AsaadW98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/AsaadW98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl1998.html#AsaadW98>
rdfs:seeAlso <https://doi.org/10.1007/BFb0055255>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document