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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/ChandrasekaranA06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abbes_Amira>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shrutisagar_Chandrasekaran>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2006.311338>
foaf:homepage <https://doi.org/10.1109/FPL.2006.311338>
dc:identifier DBLP conf/fpl/ChandrasekaranA06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2006.311338 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label FPGA Implementation and Power Modelling of the Fast Walsh Transform. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abbes_Amira>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shrutisagar_Chandrasekaran>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/ChandrasekaranA06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/ChandrasekaranA06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#ChandrasekaranA06>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2006.311338>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title FPGA Implementation and Power Modelling of the Fast Walsh Transform. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document