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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/ClarkeCC07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonathan_A._Clarke>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2007.4380653>
foaf:homepage <https://doi.org/10.1109/FPL.2007.4380653>
dc:identifier DBLP conf/fpl/ClarkeCC07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2007.4380653 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label On the feasibility of early routing capacitance estimation for FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonathan_A._Clarke>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
swrc:pages 234-239 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/ClarkeCC07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/ClarkeCC07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2007.html#ClarkeCC07>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2007.4380653>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title On the feasibility of early routing capacitance estimation for FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document