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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/DandalisPT01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_Dandalis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bharani_Thiruvengadam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F3-540-44687-7%5F33>
foaf:homepage <https://doi.org/10.1007/3-540-44687-7_33>
dc:identifier DBLP conf/fpl/DandalisPT01 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F3-540-44687-7%5F33 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_Dandalis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bharani_Thiruvengadam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
swrc:pages 315-325 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/DandalisPT01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/DandalisPT01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2001.html#DandalisPT01>
rdfs:seeAlso <https://doi.org/10.1007/3-540-44687-7_33>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document