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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/FarisiHBS11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brahim_Al_Farisi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dirk_Stroobandt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karel_Bruneel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karel_Heyse>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2011.39>
foaf:homepage <https://doi.org/10.1109/FPL.2011.39>
dc:identifier DBLP conf/fpl/FarisiHBS11 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2011.39 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
rdfs:label Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brahim_Al_Farisi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dirk_Stroobandt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karel_Bruneel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karel_Heyse>
swrc:pages 171-176 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2011>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/FarisiHBS11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/FarisiHBS11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#FarisiHBS11>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2011.39>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:subject FPGA, Run-time Reconfiguration, Tunable LUT circuit, ICAP, SRL (xsd:string)
dc:title Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document