[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/Lhairech-LebretonCM10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eric_Martin_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ghizlane_Lhairech-Lebreton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philippe_Coussy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2010.94>
foaf:homepage <https://doi.org/10.1109/FPL.2010.94>
dc:identifier DBLP conf/fpl/Lhairech-LebretonCM10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2010.94 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eric_Martin_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ghizlane_Lhairech-Lebreton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philippe_Coussy>
swrc:pages 464-468 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/Lhairech-LebretonCM10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/Lhairech-LebretonCM10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2010.html#Lhairech-LebretonCM10>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2010.94>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document