An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpl/LiuCH08
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An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
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An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
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