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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/LiuCMC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Konstantinos_Masselos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2008.4629928>
foaf:homepage <https://doi.org/10.1109/FPL.2008.4629928>
dc:identifier DBLP conf/fpl/LiuCMC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2008.4629928 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/George_A._Constantinides>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Konstantinos_Masselos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Liu>
swrc:pages 179-184 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/LiuCMC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/LiuCMC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#LiuCMC08>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2008.4629928>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document