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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/MayaRTA00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9sar_Torres-Huitzil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._Rocio_Reynoso>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Miguel_O._Arias-Estrada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Selene_Maya>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F3-540-44614-1%5F30>
foaf:homepage <https://doi.org/10.1007/3-540-44614-1_30>
dc:identifier DBLP conf/fpl/MayaRTA00 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F3-540-44614-1%5F30 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Compact Spiking Neural Network Implementation in FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9sar_Torres-Huitzil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._Rocio_Reynoso>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Miguel_O._Arias-Estrada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Selene_Maya>
swrc:pages 270-276 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/MayaRTA00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/MayaRTA00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2000.html#MayaRTA00>
rdfs:seeAlso <https://doi.org/10.1007/3-540-44614-1_30>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Compact Spiking Neural Network Implementation in FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document