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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/NguyenPP11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bogdan_Pasca_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hong_Diep_Nguyen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_B._Preu%E2%88%9A%C3%BCer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2011.49>
foaf:homepage <https://doi.org/10.1109/FPL.2011.49>
dc:identifier DBLP conf/fpl/NguyenPP11 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2011.49 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
rdfs:label FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bogdan_Pasca_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hong_Diep_Nguyen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_B._Preu%E2%88%9A%C3%BCer>
swrc:pages 232-237 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2011>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/NguyenPP11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/NguyenPP11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#NguyenPP11>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2011.49>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:subject FPGA, addition, carry-chain, carry-select, carry-increment (xsd:string)
dc:title FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document