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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/VorwerkRDHKK08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrew_A._Kennings>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arun_Kundu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Julien_Dunoyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kristofer_Vorwerk>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Madhu_Raman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yaun-Chung_Hsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL.2008.4629937>
foaf:homepage <https://doi.org/10.1109/FPL.2008.4629937>
dc:identifier DBLP conf/fpl/VorwerkRDHKK08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL.2008.4629937 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label A technique for minimizing power during FPGA placement. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrew_A._Kennings>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arun_Kundu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Julien_Dunoyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kristofer_Vorwerk>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Madhu_Raman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yaun-Chung_Hsu>
swrc:pages 233-238 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/VorwerkRDHKK08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/VorwerkRDHKK08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#VorwerkRDHKK08>
rdfs:seeAlso <https://doi.org/10.1109/FPL.2008.4629937>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title A technique for minimizing power during FPGA placement. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document