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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/WheelerGNH01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brad_L._Hutchings>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brent_E._Nelson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_S._Graham>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Timothy_Wheeler>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F3-540-44687-7%5F50>
foaf:homepage <https://doi.org/10.1007/3-540-44687-7_50>
dc:identifier DBLP conf/fpl/WheelerGNH01 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F3-540-44687-7%5F50 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brad_L._Hutchings>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brent_E._Nelson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_S._Graham>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Timothy_Wheeler>
swrc:pages 483-492 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/WheelerGNH01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/WheelerGNH01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2001.html#WheelerGNH01>
rdfs:seeAlso <https://doi.org/10.1007/3-540-44687-7_50>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document