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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpl/XiaoHPD22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aditya_Hota>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_DeHon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dongjoon_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanlong_Xiao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPL57034.2022.00022>
foaf:homepage <https://doi.org/10.1109/FPL57034.2022.00022>
dc:identifier DBLP conf/fpl/XiaoHPD22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPL57034.2022.00022 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aditya_Hota>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_DeHon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dongjoon_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanlong_Xiao>
swrc:pages 70-78 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpl/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpl/XiaoHPD22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpl/XiaoHPD22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpl/fpl2022.html#XiaoHPD22>
rdfs:seeAlso <https://doi.org/10.1109/FPL57034.2022.00022>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpl>
dc:title HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document