Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fpt/BenkridBC02
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Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs.
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Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs.
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