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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpt/EchavarriaWBTZ16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_Becher>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Ziener>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Teich>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jorge_Echavarria>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stefan_Wildermann>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPT.2016.7929536>
foaf:homepage <https://doi.org/10.1109/FPT.2016.7929536>
dc:identifier DBLP conf/fpt/EchavarriaWBTZ16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPT.2016.7929536 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_Becher>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Ziener>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Teich>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jorge_Echavarria>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stefan_Wildermann>
swrc:pages 213-216 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpt/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpt/EchavarriaWBTZ16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpt/EchavarriaWBTZ16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpt/fpt2016.html#EchavarriaWBTZ16>
rdfs:seeAlso <https://doi.org/10.1109/FPT.2016.7929536>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpt>
dc:title FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document