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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fpt/QiAC16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Benton_H._Calhoun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/He_Qi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oluseyi_A._Ayorinde>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFPT.2016.7929183>
foaf:homepage <https://doi.org/10.1109/FPT.2016.7929183>
dc:identifier DBLP conf/fpt/QiAC16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFPT.2016.7929183 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Benton_H._Calhoun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/He_Qi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oluseyi_A._Ayorinde>
swrc:pages 20-27 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fpt/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fpt/QiAC16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fpt/QiAC16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fpt/fpt2016.html#QiAC16>
rdfs:seeAlso <https://doi.org/10.1109/FPT.2016.7929183>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fpt>
dc:title An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document