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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fqas/ErbakanovKPSB15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lenko_Erbakanov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sotir_Sotirov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Todor_Kostadinov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Todor_Petkov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Veselina_Bureva>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-26211-6%5F21>
foaf:homepage <https://doi.org/10.1007/978-3-319-26211-6_21>
dc:identifier DBLP conf/fqas/ErbakanovKPSB15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-26211-6%5F21 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Modeling Logic Gates and Circuits with Generalized Nets. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lenko_Erbakanov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sotir_Sotirov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Todor_Kostadinov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Todor_Petkov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Veselina_Bureva>
swrc:pages 243-256 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fqas/2015iwifsgn>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fqas/ErbakanovKPSB15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fqas/ErbakanovKPSB15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fqas/iwifsgn2015.html#ErbakanovKPSB15>
rdfs:seeAlso <https://doi.org/10.1007/978-3-319-26211-6_21>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fqas>
dc:title Modeling Logic Gates and Circuits with Generalized Nets. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document