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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/gcce/ChangHYCT18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-Hung_Tsai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Yu_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guan-Shen_Yao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kai-Yu_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi-Hua_Chang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGCCE.2018.8574849>
foaf:homepage <https://doi.org/10.1109/GCCE.2018.8574849>
dc:identifier DBLP conf/gcce/ChangHYCT18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGCCE.2018.8574849 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Mixed-Level Design Methodology for Digitally Controlled Power Converter IC. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-Hung_Tsai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Yu_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guan-Shen_Yao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kai-Yu_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi-Hua_Chang>
swrc:pages 811-812 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/gcce/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/gcce/ChangHYCT18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/gcce/ChangHYCT18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/gcce/gcce2018.html#ChangHYCT18>
rdfs:seeAlso <https://doi.org/10.1109/GCCE.2018.8574849>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/gcce>
dc:title Mixed-Level Design Methodology for Digitally Controlled Power Converter IC. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document