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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/gcce/YehCYT23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-Hung_Tsai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Lun_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shang-Chih_Yin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Ting_Yeh>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGCCE59613.2023.10315270>
foaf:homepage <https://doi.org/10.1109/GCCE59613.2023.10315270>
dc:identifier DBLP conf/gcce/YehCYT23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGCCE59613.2023.10315270 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-Hung_Tsai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Lun_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shang-Chih_Yin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Ting_Yeh>
swrc:pages 1172-1175 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/gcce/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/gcce/YehCYT23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/gcce/YehCYT23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/gcce/gcce2023.html#YehCYT23>
rdfs:seeAlso <https://doi.org/10.1109/GCCE59613.2023.10315270>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/gcce>
dc:title Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document