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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/Abu-KhaterBEY95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abdellatif_Bellaouar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Issam_S._Abu-Khater>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohamed_I._Elmasry>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ran-Hong_Yan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516028>
foaf:homepage <https://doi.org/10.1109/GLSV.1995.516028>
dc:identifier DBLP conf/glvlsi/Abu-KhaterBEY95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGLSV.1995.516028 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Circuit/architecture for low-power high-performance 32-bit adder. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abdellatif_Bellaouar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Issam_S._Abu-Khater>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohamed_I._Elmasry>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ran-Hong_Yan>
swrc:pages 74- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/Abu-KhaterBEY95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/Abu-KhaterBEY95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#Abu-KhaterBEY95>
rdfs:seeAlso <https://doi.org/10.1109/GLSV.1995.516028>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject adders; CMOS logic circuits; integrated circuit design; circuit optimisation; logic design; adder; conditional sum architecture; CPL-like logic implementation; power supply voltage; minimum size; optimized speed; CMOS; 32 bit; 1 to 3.3 V (xsd:string)
dc:title Circuit/architecture for low-power high-performance 32-bit adder. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document